In a known manner, synchronous logic integrated circuits require a clock signal to synchronize operation of the logic elements of the circuit. Typically, this clock signal is distributed from a clock signal generator to elements of the circuit, such as registers or switches, by way of a clock tree. This clock tree is a network of electrical interconnects that typically has a tree-like structure, including a common trunk, connected to the clock signal generator. A multitude of branches divides off of this common trunk. Each of these branches can itself divide into a plurality of additional branches.
To ensure correct operation of the circuit, and especially to prevent setup and hold time violations, this clock tree must be carefully configured to limit the appearance of differences in the propagation time of the clock signal. These differences result in clock skew.
To avoid clock skew, the clock tree typically comprises clock tree cells that implement functions optimizing the distribution of the clock signal. Examples of such functions are buffer functions. Thus, each clock tree cell is connected to a branch of the clock tree and receives an input clock signal from this clock tree. This clock tree cell is also adapted to deliver an output clock signal for distribution to the logic elements of the circuit. In the case where the clock tree cell acts as a buffer, the output clock signal is identical to the input clock signal except that it is delayed by a pre-set amount of time. These buffers may be adapted, during design of the integrated circuit, to balance the branches of the clock tree and control the appearance of clock skew.
Typically, the circuit also comprises logic cells that contain transistors connected to form the logic elements of the circuit. Clock-tree cells located at the ends of the branches are electrically connected to the logic cells in order to transmit the output clock signal to them. These clock-tree cells located at the ends of the branches are clock-tree leaves.
As used herein, the term “standard cell” is understood to mean an integrated-circuit portion corresponding to the physical implementation of an elementary function. These standard cells result from models typically collected in an integrated circuit design software library. Standard cells can be differentiated from each other, for example, by the binary functions performed, or by their fan-out. In this patent application, a distinction is made between functional standard cells, used for the production of the logic functions of the circuit, and standard clock tree-cells. The former will be referred to as “logic cells,” whereas the latter will be referred to as “clock cells.”
Clock cells can differ from logic cells by particular characteristics such as the balancing of the rising and falling buffers, or else by a greater fan-out. The clock-tree cells conventionally used are structurally similar to the logic cells of the circuit. The leaf cells of the clock tree are preferably incorporated as close as possible to the logic cells, notably to reduce the length of the electrical connections connecting these leaf cells to the neighboring logic cells.
Nowadays, it is desirable to reduce the power consumption of integrated circuit devices, for example for nomadic IT applications. It is thus necessary to be able to make integrated circuits operate in specific low energy consumption modes, wherein the power supply voltage is reduced to an ultra-low voltage.
However, the reduction of the power supply voltage of such a circuit can cause deterioration in the performance of the clock tree. This deterioration originates, for example, from a greater sensitivity of the clock tree to variability in the fabrication process of the transistors, when the circuit is electrically powered with a supply voltage of reduced value. This greater sensitivity leads to a rise in the time constraint violations. It is then necessary to modify the clock tree by adding several elements to it, such as delays. This tends to complicate the design and the fabrication of the circuit.
A need therefore exists for an integrated circuit comprising a clock-tree cell whose performance has better robustness when the integrated circuit is powered with an electrical voltage of reduced value.